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Peripheral controllers for individual LED panels

There are a few options for both the processors themselves and the configurations they go in to. The easiest for implementation would likely be the rp2040 / rp2350, due to their simple structures and requirements, as well as a very simple programming potential. Other options include items such as the low power ESP32 packages, STM32, nRF52840, such and such.

Alternatively, this can be done entirely with a small to moderate FPGA. Rather than programming six of one processor, only a single FPGA is loaded and provided the logic to control the LED panels. FPGAs also provide the ability for me to challenge my knowledge on Verilog and VHDL implementation, which is a plus.

Number of GPIOs total is also important. Each panel needs 13-14 GPIOs for the signals. For one shared processor, the CLK, LAT, OE, and Row Adress lines, with 6x of the pixel data pins (6x pins), for a total of 44 GPIOs.

The peripheral device will be important for the internal pixel refresh rate, which has a target refresh rate of 1000Hz. The peripheral device needs to be able to drive these refreshes fast enough to not cause flicker.

Speed Calculation for Pixel Refresh

Given: - 64 LEDs per column (per panel) - 64 columns - 6 bits per clock (R1, G1, B1, R2, G2, B2) - 32 row addresses (2 at a time) - At max, 8 bit color, 8 bitplanes - At min, 1 bit color, 1 bitplane

Calculation: 

    32 row * 8 bitplane * 1000Hz = 256000 row scan / sec
    256000 row scans / s * 64 clocks / row = 16,384,000 clocks/s at max

    32 row * 1 bitplane * 1000Hz = 32000 row scan /s
    32000 row scans /s * 64 clocks / row = 2,048,000 clocks/s at min
Pixel refresher would run at 16.4MHz at maximum, 2MHz at minimum.

Key Requirements

  • 2MB flash (internal or external)

  • SPI communication bus to communicate with host
  • USB or UART flash options
  • Small package size

Processor Options

  • RP2040
    • Dual Core 133MHz
    • 264kB SRAM
    • USB connectivity
    • 7mm x 7mm QFN-56, no flash
  • RP2350
    • Dual Core 150MHz
    • 520kB SRAM
    • USB Connectivity
    • RP2350A: 30 GPIO, 7x7 QFN60, no flash
    • RP2350B: 48 GPIO, 10x10 QFN80, no flash
    • RP2354A: 30 GPIO, 7x7 QFN60, 2MB stacked flash
    • RP2354B: 48 GPIO, 10x10 QFN80, 2MB stacked flash
  • Lattice iCE40
    • MAX 39 IO -- DISQUALIFIED
    • Good for single channel development, though
  • Lattice ECP5
    • 98-365 GPIO (entirely unnecessary amounts)
    • Extra research required to determine effecacy of FPGA For this project

A dev board for the iCE40 has been ordered to test the functionality and reliability of FPGAs. If this does not work, then a few other things will need to change as well.